FIG. 1 is a partial block diagram of a conventional synchronous semiconductor memory including circuits related to a data input device. FIG. 2 is a circuit diagram of a data register for the memory device shown in FIG. 1. FIG. 3 is a timing diagram of a data writing operation for the memory device shown in FIG. 1.
Referring to FIG. 1, a data input circuit 110 includes a data input buffer 100, an edge detector 101, a data register 102, and a write driver 103. The data register 102 includes a pair of latches L1 and L2 respectively controlled by a clock signal .phi.CLK and a complementary clock signal .phi.CLK as best shown in FIG. 21. Data DIN.sub.M (where M is equal to 0, 1, 3, . . . i) is input externally to the data buffer 100. The data buffer 100 provides the buffered data signal DIND.sub.M to the data registers to meet the requirement of set-up and hold times on the basis of a rising edge of the clock signal .phi.CLK generated from the edge detector 101. The data string DIND.sub.M generated from the data input buffer 100 is sampled by the latches L1 and L2. The latches L1 and L2 are synchronized with the clock signals .phi.CLK and .phi.CLK, respectively, and then applied to the write driver 103. The externally applied address and write commands are decoded by an ADD&COM buffer 104, an ADD&COM decoder 105, and a timing control circuit 106. The write driver 103 activates the decoded signals. The write driver 103 delivers the data string DIND.sub.M from the data register 102 to a data line. Also, a column decoder 107 generates a column selection signal CSL used to select a column of the memory array corresponding to an input address responsive to the timing control circuit 106. Thus, during a data writing operation, one data signal is written into the memory device every clock cycle.
However, recently developed high-speed processors and multimedia computer systems require memory devices having higher and higher bandwidths. A technique has been developed to address these needs. The technique involves reading or writing data from or into memory cell array, respectively, by using both the rising and falling edges of the clock signal. This technique is frequently called Double Data Rate (DDR).
In addition, there is a technique for providing a data strobe signal together with a data signal transferred to meet the requirement of set-up time and hold time of its destination. This transfer of data and strobe signals can easily be achieved by toggling a dummy data signal. By doing so, during a data writing operation, two or four data signals may be written into respective memory cell arrays every clock cycle during a writing operation according to a variety of writing methods.